1. Field of the Invention
The present invention generally relates to sensors for detecting charging problems during ion implantation and/or plasma processes.
2. Description of the Related Art
During semiconductor wafer manufacturing, ion implantation or plasma-assisted processes may cause positive or negative charges to accumulate on insulators or conductors (e.g., floating conductors) because of non-uniformities in beam and plasma neutrality.
Typical plasma processes include Reactive Ion Etching (RIE) and Plasma Enhanced Chemical Vapor Deposition (PECVD). Use of High-density plasma, such as Electron Cyclotron Resonance (ECR) and Inductive Coupling Plasma (ICP) can exacerbate the problem of charge accumulation. When the charge reaches a critical level of approximately 2.times.10.sup.13 charges/cm2, the insulator can be permanently damaged.
The charge accumulation problem is amplified by an unavoidable antenna effect caused by antenna ratios of varying magnitudes. The antenna ratio (AR) is the ratio of conductor area of thick oxide to conductor area over thin oxide. Amplification of charge caused by high antenna ratios can damage the gate dielectric at an average surface charge concentration considerably below the critical level.
At the design level, antenna ratios are limited to a maximum of 100:1-400:1 to reduce charge amplification over the thin oxides. Some designs do not allow photoresist masks to overlap the gate conductor (typically a gate stack) to avoid further amplification of charge over thin dielectrics. These precautionary measures are, however, done at the cost of circuit density, speed, and interconnection flexibility.
These undesirable charging effects are referred as "Ion Implantation Charging" or "Plasma Damage". Several tool, integration, and design techniques have been implemented to reduce charging damage. Such techniques include more efficient tuning of plasma conditions and the use of a "Flood-Gun" or "Plasma-Gun" to neutralize the ion beam. Integration techniques, such as the use of buried contacts to provide a leakage path for charges, also reduce the effect of charging. However, such techniques increase processing complexity and decrease circuit performance.
A sensor that simulates the actual wafer being processed and monitors the tool beam and plasma potentials can be used during wafers processing. Such a sensor is placed in the chamber with the wafer during processing to detect any charge accumulation. Conventional systems utilize two types of sensors to detect charging problems.
The first is a MOS and/or MOSFET structure which has different antenna ratios. The second sensor type is based on EEPROM, i.e. MOSFETs with floating and control gates that can be programmed to sense voltages caused by "charging" (CHARM-2) described in U.S. Pat. No. 5,315,145 issued to Wieslaw A. Lukaszeek, entitled "Charge Sensoring Device for Use in Semiconductor Wafer Fabrication for Unipolar Operation and Charge Sensoring", dated May 24, 1994, incorporated herein by reference.
However, there are drawbacks associated with both of these types of sensors. The MOS/MOSFET sensors detect only oxide and interface degradations and relate these degradations to the presence of charges without providing information on the magnitude of charge and on potential distributions. Also, the structures are only accessible after some level of processing and are typically not reusable.
While CHARM-2 sensors are reusable and detect potential distributions across the wafer, they require complex processing of the EEPROM structures. Also, these structures contain layers and surfaces different from those of the actual product. In other words, CHARM-2 sensors do not closely simulate the wafer being produced. Another disadvantage of CHARM-2 is the wafer size. Presently, only 150-mm wafers are available. Preparing 200-300 mm CHARM-2 wafers is costly.